1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and, more particularly, to methods of fabricating FinFET device structures.
2. Description of the Related Art
The FinFET device in general is well known. The FinFET device is one of the technical alternatives to planar transistors, in order to continue scaling down the sizes of transistors—for example, to 32 nm and smaller.
In general, a FinFET device is a non-planar, double gate transistor formed on a substrate such as a silicon-on-insulator (SOI) substrate. In the FinFET device, an electrically conductive channel is wrapped around a thin semiconductor (e.g., silicon) “fin” which forms a body of the device. The dimensions of the fin essentially determine an effective channel length of the device.
A gate including a metal conductor and a high-k dielectric further helps scaling by reducing polysilicon depletion and gate leakage.
To help meet different requirements of FinFET devices, it is sometimes desirable to have multiple FinFET devices with different characteristics such as different threshold voltages (Vt) formed on a same SOI substrate.
FinFET device structures with multiple devices having metal conductor and high-k insulator gates formed on the same semiconductor or SOI substrate are known. See, for example:
U.S. Pat. No. 7,105,390 B2, filed Dec. 30, 2003, issued Sep. 12, 2006, NON PLANAR TRANSISTORS WITH METAL GATE ELECTRODES, by Justin K. Brask et al.; U.S. Pat. No. 7,187,046 B2, filed Apr. 26, 2004, issued Mar. 6, 2007, METHOD OF FORMING AN N CHANNEL AND P CHANNEL FINFET DEVICE ON THE SAME SEMICONDUCTOR SUBSTRATE, by Chung-Chen Wu et al.
Although the known FinFET devices and methods of their manufacture are helpful, the present inventors believe that further improvements (e.g., cost, flexibility) in methods of manufacturing FinFET devices on the same substrate are achievable.